Memory device and method of operating the same

ABSTRACT

A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean patent application number 10-2020-0138382 filed on Oct. 23, 2020,in the Korean Intellectual Property Office, the entire disclosure ofwhich is incorporated by reference herein.

BACKGROUND 1. Technical Field

Various embodiments of the present disclosure generally relate to anelectronic device, and more particularly to a memory device and a methodof operating the memory device.

2. Related Art

A storage device is a device which stores data under the control of ahost device such as a computer, a smartphone, or a smartpad. Examples ofa storage device include a device such as a hard disk drive (HDD) whichstores data in a magnetic disk, and a device such as a solid state drive(SSD) or a memory card which stores data in semiconductor memory,particularly, nonvolatile memory, according to the device in which datais stored.

The storage device may include a memory device in which data is storedand a memory controller which controls the storage of the data in thememory device. Such memory devices may be classified as a volatilememory device or a nonvolatile memory device. Representative examples ofnonvolatile memory include read only memory (ROM), programmable ROM(PROM), electrically programmable ROM (EPROM), electrically erasableprogrammable ROM (EEPROM), flash memory, phase-change random accessmemory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), andferroelectric RAM (FRAM).

SUMMARY

Various embodiments of the present disclosure are directed to a memorydevice that increases a data input speed when data is input using onlysome of a greater number of input/output lines, and a method ofoperating the memory device.

In accordance with an embodiment of the present disclosure is a memorydevice including a plurality of pages, a peripheral, and control logic.The peripheral circuit is configured to receive a command, an address,and data from an external controller to program a page selected fromamong the plurality of pages, and to generate internal input datadepending on an input mode for the command, the address, and the data.The control logic is configured to determine whether internal input datais to be generated based on the data depending on the input mode and tocontrol the peripheral circuit so that a program operation ofprogramming the internal input data is performed.

In accordance with another embodiment of the present disclosure is amemory device including a plurality of pages, a mode setter, and inputcontroller, and a control signal generator. The mode setter isconfigured to set a mode in which a command, an address, and data arereceived from an external controller to program a page selected fromamong the plurality of pages. The input controller is configured togenerate internal input data based on the data depending on the mode setby the mode setter, and the control signal generator is configured togenerate a control signal for controlling the input controller togenerate the internal input data.

In accordance with an additional embodiment of the present disclosure isa method of operating a memory device. The method includes setting amode in which a command, an address, and data are received from anexternal controller to program a page selected from among a plurality ofpages. The method also includes receiving the data based on the setmode, generating a control signal for generating internal input databased on the data depending on the set mode, and generating the internalinput data based on the control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a storage device.

FIG. 2 is a diagram illustrating a structure of a memory device of FIG.1.

FIG. 3 is a diagram illustrating an embodiment of a memory cell array ofFIG. 2.

FIG. 4 is a diagram for describing a pin configuration of the memorydevice of FIG. 1.

FIG. 5 is a diagram illustrating an embodiment in which a memory deviceand a test device are coupled to each other during a test operation.

FIG. 6 is a diagram illustrating an embodiment in which a memory deviceis coupled to a test device during a test operation.

FIG. 7 illustrates a method in which data is input to a plurality ofdies during the test operation of FIG. 6.

FIG. 8 is a timing diagram illustrating a process in which a command, anaddress, and data are input in an X8 mode.

FIG. 9 is a timing diagram illustrating a process in which data is inputin an X4 mode.

FIG. 10 illustrates a method of reducing a data input time in an X4mode.

FIGS. 11A to 11C illustrate methods in which data is input in an X4 modeand an X8 mode.

FIG. 12 illustrates control signals required for data input andgenerated internal input data in an X4 mode.

FIG. 13 illustrates the configuration of a control signal generator forgenerating a fast mode signal of FIG. 12.

FIG. 14 is a flowchart illustrating the operation of a memory deviceaccording to an embodiment of the present disclosure.

FIG. 15 is a diagram illustrating an embodiment of the memory controllerof FIG. 1.

FIG. 16 is a block diagram illustrating a memory card system to which astorage device according to an embodiment of the present disclosure isapplied.

FIG. 17 is a block diagram illustrating a solid state drive (SSD) systemto which a storage device according to an embodiment of the presentdisclosure is applied.

FIG. 18 is a block diagram illustrating a user system to which a storagedevice according to an embodiment of the present disclosure is applied.

DETAILED DESCRIPTION

Specific structural or functional descriptions in the embodiments of thepresent disclosure introduced in this specification or application areonly for description of the embodiments of the present disclosure. Thedescriptions should not be construed as being limited to the embodimentsdescribed in the specification or application.

Various embodiments of the present disclosure will now be described morefully hereinafter with reference to the accompanying drawings, in whichembodiments of the present disclosure are illustrated, so that those ofordinary skill in the art can carry out the technical idea of thepresent disclosure.

FIG. 1 is a block diagram illustrating a storage device.

Referring to FIG. 1, a storage device 50 may include a memory device 100and a memory controller 200.

The storage device 50 may be a device which stores data under thecontrol of a host 300, such as a mobile phone, a smartphone, an MP3player, a laptop computer, a desktop computer, a game console, atelevision (TV), a tablet PC, or an in-vehicle infotainment system.

The storage device 50 may be manufactured as any one of various types ofstorage devices depending on a host interface that is a scheme forcommunication with the host 300. For example, the storage device 50 maybe implemented as any one of various types of storage devices, forinstance, a solid state disk (SSD); a multimedia card such as an MMC, anembedded MMC (eMMC), a reduced size MMC (RS-MMC), or a micro-MMC; asecure digital card such as an SD, a mini-SD, or a micro-SD; a universalserial bus (USB) storage device; a universal flash storage (UFS) device;a personal computer memory card international association (PCMCIA)card-type storage device; a peripheral component interconnection(PCI)-card type storage device; a PCI express (PCI-E) card-type storagedevice; a compact flash (CF) card; a smart media card; and a memorystick.

The storage device 50 may be manufactured in any one of various types ofpackage forms. For example, the storage device 50 may be manufactured asa package on package (POP), a system in package (SIP), a system on chip(SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-levelfabricated package (WFP), or a wafer-level stack package (WSP).

The memory device 100 may store data. The memory device 100 is operatedin response to the control of the memory controller 200. The memorydevice 100 may include a memory cell array including a plurality ofmemory cells which store data. The memory cell array may include aplurality of memory blocks. Each memory block may include a plurality ofmemory cells, which may constitute a plurality of pages. In anembodiment, each page may be a unit by which data is stored in thememory device 100 or by which data stored in the memory device 100 isread. A memory block may be a unit by which data is erased.

In an embodiment, the memory device 100 may take many alternative forms,such as including double data rate synchronous dynamic random accessmemory (DDR SDRAM), low power double data rate fourth generation(LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR(LPDDR) SDRAM, Rambus dynamic random access memory (RDRAM), NAND flashmemory, vertical NAND flash memory, NOR flash memory device, resistiveRAM (RRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM),ferroelectric RAM (FRAM), or spin transfer torque RAM (STT-RAM). In thepresent specification, for convenience of description, it is assumedthat the memory device 100 includes NAND flash memory.

The memory device 100 may be implemented in a two-dimensional (2D) arraystructure or a three-dimensional (3D) array structure. Hereinafter,although a 3D array structure is described as an embodiment, the presentdisclosure is not limited to the 3D array structure. The presentdisclosure may also be applied not only to a flash memory device inwhich a charge storage layer is formed of a conductive floating gate(FG), but also to a charge trap flash (CTF) memory device in which acharge storage layer is formed of an insulating layer.

In an embodiment, the memory device 100 may be operated in asingle-level cell (SLC) manner in which one data bit is stored in onememory cell. Alternatively, the memory device 100 may be operated in amanner in which at least two data bits are stored in one memory cell.For example, the memory device 100 may be operated in a multi-level cell(MLC) manner in which two data bits are stored in one memory cell, atriple-level cell (TLC) manner in which three data bits are stored inone memory cell, or a quadruple-level cell (QLC) manner in which fourdata bits are stored in one memory cell.

The memory device 100 may receive a command and an address from thememory controller 200, and may access the area of the memory cell arrayselected by the address. That is, the memory device 100 may perform anoperation corresponding to the command on the area selected by theaddress. For example, the memory device 100 may perform a writeoperation (i.e., program operation), a read operation, or an eraseoperation in response to the received command. When a program command isreceived, the memory device 100 may program data to the area selected bythe address. When a read command is received, the memory device 100 mayread data from the area selected by the address. When an erase commandis received, the memory device 100 may erase data stored in the areaselected by the address.

In an embodiment, the memory device 100 may include a mode setter 150.The mode setter 150 may set input/output modes for using all or some ofthe input/output lines coupled to the memory device 100.

In detail, when data is input/output using all of the input/output linescoupled to the memory device 100, an input/output mode may be an X8mode. However, when data is input/output using half of the input/outputlines coupled to the memory device 100, the input/output mode may be anX4 mode. Therefore, the mode setter 150 may set the X4 mode or the X8mode based on the number of lines determined to input/output data by thememory device 100.

The mode setter 150 may generate a line enable signal TM_X4_MODE in ahigh state so as to set the X4 mode or the X8 mode. For example, whenthe line enable signal TM_X4_MODE makes a transition from a low state toa high state, the memory device 100 may input/output data in the X4mode. As used herein, a signal, such the line enable signal TM_X4_MODE,having a high state distinguishes from the signal when it has a lowstate. The high and low states may represent different logic states. Forexample, the high state may correspond to the signal having a firstvoltage, and the low state may correspond to the signal having a secondvoltage. For some embodiments, the first voltage is greater than thesecond voltage. In other embodiments, different characteristics of asignal, such as frequency or amplitude, determine whether the signal isin a high state or a low state. For some cases, the high and low statesof a signal represent logical binary states.

In an embodiment, when a test operation is performed on the memorydevice 100, the mode setter 150 may set input/output lines for couplingthe memory device 100 to a test device (test equipment). Therefore,during a test operation, the mode setter 150 may set the input/outputmode of the memory device 100 to the X4 mode or the X8 mode.

In an embodiment, the memory device 100 may include an input controller170. The input controller 170 may generate new data based on input datawhen the data is input using only some of the input/output lines coupledto the memory device 100.

The time required for data input may be reduced by inputting the newdata, generated by the input controller 170 based on the data receivedthrough some lines, to the memory device 100. That is, when data isinput through some lines, a lot of time may be taken compared to thecase where data is input through all lines, but such data input time maybe reduced through data control by the input controller 170.

In an embodiment, a control signal generator 190 may generate a controlsignal for controlling the input controller 170 to generate new databased on the data received through some input/output lines. Here, thecontrol signal generator 190 may generate a fast mode signal X4_FASTLOADor a normal mode signal X4_CURRENT.

In detail, when the control signal generator 190 generates the fast modesignal X4_FASTLOAD and outputs the same to the input controller 170, theinput controller 170 may generate new data based on the data receivedthrough some lines. However, when the control signal generator 190generates the normal mode signal X4_CURRENT and outputs the same to theinput controller 170, the input controller 170 may output the datareceived through all lines without change.

The memory controller 200 may control the overall operation of thestorage device 50.

When a supply voltage is applied to the storage device 50, the memorycontroller 200 may run firmware. When the memory device 100 is a flashmemory device 100, the memory controller 200 may run firmware such as aFlash Translation Layer (FTL) for controlling communication between thehost 300 and the memory device 100.

In an embodiment, the memory controller 200 may include firmware (notillustrated) which may receive data and a logical block address (LBA)from the host 300, and may translate the logical block address (LBA)into a physical block address (PBA) indicating the address of memorycells which are included in the memory device 100 and in which data isto be stored. Further, the memory controller 200 may store alogical-physical address mapping table, which configures mappingrelationships between logical block addresses (LBA) and physical blockaddresses (PBA), in a buffer memory.

The memory controller 200 may control the memory device 100 so that aprogram operation, a read operation, or an erase operation is performedin response to a request received from the host 300. For example, when aprogram request is received from the host 300, the memory controller 200may convert the program request into a program command, and may providethe program command, a physical block address (PBA), and data to thememory device 100. When a read request together with a logical blockaddress is received from the host 300, the memory controller 200 mayconvert the read request into a read command, select a physical blockaddress corresponding to the logical block address, and thereafterprovide the read command and the physical block address (PBA) to thememory device 100. When an erase request together with a logical blockaddress is received from the host 300, the memory controller 200 mayconvert the erase request into an erase command, select a physical blockaddress corresponding to the logical block address, and thereafterprovide the erase command and the physical block address (PBA) to thememory device 100.

In an embodiment, the memory controller 200 may autonomously generate aprogram command, an address, and data without receiving a request fromthe host 300, and may transmit them to the memory device 100. Forexample, the memory controller 200 may provide commands, addresses, anddata to the memory device 100 so as to perform background operations,such as a program operation for wear leveling and a program operationfor garbage collection.

In an embodiment, the storage device 50 may include buffer memory (notillustrated). The memory controller 200 may control data exchangebetween the host 300 and the buffer memory (not illustrated).Alternatively, the memory controller 200 may temporarily store systemdata for controlling the memory device 100 in the buffer memory. Forexample, the memory controller 200 may temporarily store data, inputfrom the host 300, in the buffer memory, and may then transmit the data,temporarily stored in the buffer memory, to the memory device 100.

In various embodiments, the buffer memory may be used as working memoryor cache memory for the memory controller 200. The buffer memory maystore codes or commands that are executed by the memory controller 200.Alternatively, the buffer memory may store data that is processed by thememory controller 200.

In an embodiment, the buffer memory may be implemented as DRAM such as adouble data rate SDRAM (DDR SDRAM), double data rate fourth generation(DDR4) SDRAM, low power double data rate fourth generation (LPDDR4)SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR)SDRAM, or Rambus DRAM (RDRAM), or as static RAM (SRAM).

In various embodiments, the buffer memory may be coupled to the storagedevice 50 outside the storage device 50. In this case, volatile memorydevices coupled to the outside of the storage device 50 may function asthe buffer memory.

In an embodiment, the memory controller 200 may control at least twomemory devices. In this case, the memory controller 200 may control thememory devices depending on an interleaving scheme to improve operatingperformance.

The host 300 may communicate with the storage device 50 using at leastone of various communication methods, such as Universal Serial Bus(USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), HighSpeed Interchip (HSIC), Small Computer System Interface (SCSI),Peripheral Component Interconnection (PCI), PCI express (PCIe),Nonvolatile Memory express (NVMe), Universal Flash Storage (UFS), SecureDigital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-lineMemory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM(LRDIMM) communication methods.

FIG. 2 is a diagram illustrating the structure of the memory device 100of FIG. 1.

Referring to FIG. 2, the memory device 100 may include a memory cellarray 110, a peripheral circuit 120, and control logic 130.

The memory cell array 110 includes a plurality of memory blocks BLK1 toBLKz. The plurality of memory blocks BLK1 to BLKz are coupled to a rowdecoder 121 through row lines RL. Each of the memory blocks BLK1 to BLKzmay be coupled to a page buffer group 123 through bit lines BL1 to BLn.Each of the memory blocks BLK1 to BLKz may include a plurality of memorycells. In an embodiment, the plurality of memory cells may benonvolatile memory cells. Memory cells coupled to the same word line maybe defined as a single page. Therefore, a single memory block mayinclude a plurality of pages.

The row lines RL may include at least one source select line, aplurality of word lines, and at least one drain select line.

Each of the memory cells included in the memory cell array 110 may beimplemented as a single-level cell (SLC) capable of storing one databit, a multi-level cell (MLC) capable of storing two data bits, atriple-level cell (TLC) capable of storing three data bits, or aquadruple-level cell (QLC) capable of storing four data bits.

The peripheral circuit 120 may perform a program operation, a readoperation, or an erase operation on a selected area of the memory cellarray 110 under the control of the control logic 130. The peripheralcircuit 120 may drive the memory cell array 110. For example, theperipheral circuit 120 may apply various operating voltages to the rowlines RL and the bit lines BL1 to BLn or discharge the applied voltagesunder the control of the control logic 130.

The peripheral circuit 120 may include the row decoder 121, a voltagegenerator 122, the page buffer group 123, a column decoder 124, aninput/output circuit 125, and a sensing circuit 126.

The row decoder 121 is coupled to the memory cell array 110 through therow lines RL. The row lines RL may include the at least one sourceselect line, the plurality of word lines, and the at least one drainselect line. In an embodiment, the word lines may include normal wordlines and dummy word lines. In an embodiment, the row lines RL mayfurther include a pipe select line.

The row decoder 121 may decode a row address RADD received from thecontrol logic 130. The row decoder 121 selects at least one of thememory blocks BLK1 to BLKz according to the decoded address. Further,the row decoder 121 may select at least one word line WL of the selectedmemory block so that voltages generated by the voltage generator 122 areapplied to the at least one word line WL according to the decodedaddress.

For example, during a program operation, the row decoder 121 may apply aprogram voltage to a selected word line and apply a program pass voltagehaving a level lower than that of the program voltage to unselected wordlines. During a program verify operation, the row decoder 121 may applya verify voltage to a selected word line and apply a verify pass voltagehigher than the verify voltage to unselected word lines. During a readoperation, the row decoder 121 may apply a read voltage to a selectedword line and apply a read pass voltage higher than the read voltage tounselected word lines.

In an embodiment, the erase operation of the memory device 100 isperformed on a memory block basis. During an erase operation, the rowdecoder 121 may select one memory block according to the decodedaddress. During the erase operation, the row decoder 121 may apply aground voltage to word lines coupled to the selected memory block.

The voltage generator 122 may be operated under the control of thecontrol logic 130. The voltage generator 122 may generate a plurality ofvoltages using an external supply voltage provided to the memory device100. In detail, the voltage generator 122 may generate various operatingvoltages Vop that are used for program, read, and erase operations inresponse to an operation signal OPSIG. For example, the voltagegenerator 122 may generate a program voltage, a verify voltage, a passvoltages, a read voltage, an erase voltage, etc. under the control ofthe control logic 130.

In an embodiment, the voltage generator 122 may generate an internalsupply voltage by regulating the external supply voltage. The internalsupply voltage generated by the voltage generator 122 is used as anoperating voltage for the memory device 100.

In an embodiment, the voltage generator 122 may generate a plurality ofvoltages using the external supply voltage or the internal supplyvoltage.

For example, the voltage generator 122 may include a plurality ofpumping capacitors for receiving the internal supply voltage andgenerate a plurality of voltages by selectively enabling the pluralityof pumping capacitors under the control of the control logic 130.

The generated voltages may be supplied to the memory cell array 110 bythe row decoder 121.

The page buffer group 123 includes first to nth page buffers PB1 to PBn.The first to nth page buffers PB1 to PBn are coupled to the memory cellarray 110 through the first to nth bit lines BL1 to BLn. The first tonth page buffers PB1 to PBn are operated under the control of thecontrol logic 130. In detail, the first to nth page buffers PB1 to PBnmay be operated in response to page buffer control signals PBSIGNALS.For example, the first to nth page buffers PB1 to PBn may temporarilystore data received through the first to nth bit lines BL1 to BLn or maysense voltages or currents of the bit lines BL1 to BLn during a read orverify operation.

In detail, during a program operation, when the program voltage isapplied to the selected word line, the first to nth page buffers PB1 toPBn may transfer the data DATA, received through the input/outputcircuit 125, to selected memory cells through the first to nth bit linesBL1 to BLn. The memory cells in the selected page are programmed basedon the received data DATA. During a program verify operation, the firstto nth page buffers PB1 to PBn may read page data by sensing thevoltages or currents received through the first to nth bit lines BL1 toBLn from the selected memory cells.

During a read operation, the first to nth page buffers PB1 to PBn mayread data DATA from the memory cells in the selected page through thefirst to nth bit lines BL1 to BLn, and may output the read data DATA tothe input/output circuit 125 under the control of the column decoder124.

During the erase operation, the first to nth page buffers PB1 to PBn mayallow the first to nth bit lines BL1 to BLn to float or may apply theerase voltage to the first to nth bit lines BL1 to BLn.

The column decoder 124 may transfer data between the input/outputcircuit 125 and the page buffer group 123 in response to a columnaddress CADD. For example, the column decoder 124 may exchange data withthe first to nth page buffers PB1 to PBn through data lines DL or mayexchange data with the input/output circuit 125 through column lines CL.

The input/output circuit 125 may transfer a command CMD and an addressADDR, received from the memory controller (e.g., 200 of FIG. 1)described above with reference to FIG. 1, to the control logic 130, ormay exchange data DATA with the column decoder 124.

During a read operation or a verify operation, the sensing circuit 126may generate a reference current in response to an enable bit VRYBIT,and may compare a sensing voltage VPB received from the page buffergroup 123 with a reference voltage generated by the reference currentand then output a pass signal PASS or a fail signal FAIL.

The control logic 130 may control the peripheral circuit 120 byoutputting the operation signal OPSIG, the row address RADD, the pagebuffer control signals PBSIGNALS, and the enable bit VRYBIT in responseto the command CMD and the address ADDR. For example, the control logic130 may control a read operation on a selected memory block in responseto a sub-block read command and an address. Also, the control logic 130may control an erase operation on a selected sub-block included in aselected memory block in response to a sub-block erase command and anaddress. In addition, the control logic 130 may determine whether averify operation has passed or failed in response to the pass or failsignal PASS or FAIL. The control logic 130 may be implemented ashardware, software, or a combination of hardware and software. Forexample, the control logic 130 may be a control logic circuit operatingin accordance with an algorithm and/or a processor executing controllogic code.

In an embodiment, the control logic 130 may include a mode setter 150and a control signal generator 190, and the input/output circuit 125 mayinclude an input controller 170. In other embodiments, the mode setter150 and the control signal generator 190 may be provided outside thecontrol logic 130. In other embodiments, the input controller 170 may beprovided outside the input/output circuit 125.

In an embodiment, the mode setter 150 may output a line enable signalTM_X4_MODE to the control signal generator 190, and the control signalgenerator 190 may output a fast mode signal X4_FASTLOAD for controllingdata input to the input controller 170 based on the line enable signalTM_X4_MODE.

In an embodiment, when the memory device 100 is operated in an X8 mode,the line enable signal TM_X4_MODE may be output as a low-state signal tothe control signal generator 190, whereas when the memory device isoperated in an X4 mode, the line enable signal TM_X4_MODE may be outputas a high-state signal to the control signal generator 190. Here,assuming that the total number of input/out lines coupled between thememory device 100 and the memory controller (e.g., 200 of FIG. 1) is 8,the data input mode may be the X8 mode when data is received through allof the input/output lines, and may be the X4 mode when data is receivedthrough four input/output lines that are some of all the input/outputlines.

In an embodiment, when the control signal generator 190 receives theline enable signal TM_X4_MODE in a high state in the X4 mode, thecontrol signal generator 190 may generate a control signal forgenerating internal input data based on the data received through someinput/output lines. The control signal for generating internal inputdata may be a fast mode signal X4_FASTLOAD. The fast mode signalX4_FASTLOAD may indicate the input start of data X4_MODE_START and theinput end of data X4_MODE_END in the X4 mode.

In an embodiment, the input controller 170 may generate internal inputdata based on the fast mode signal X4_FASTLOAD. In detail, when data isreceived from an external controller through some input/output lines inthe X4 mode, the input controller 170 may generate the internal inputdata. The generated internal input data may be programmed to memorycells in a selected page.

FIG. 3 is a diagram illustrating an embodiment of the memory cell arrayof FIG. 2.

Referring to FIGS. 2 and 3, FIG. 3 is a circuit diagram illustrating anyone memory block BLKa of a plurality of memory blocks BLK1 to BLKzincluded in the memory cell array 110 of FIG. 2.

The memory block BLKa may be coupled to a first select line, word lines,and a second select line that are coupled in parallel to each other. Forexample, the word lines may be coupled in parallel to each other betweenthe first and second select lines. Here, the first select line may be asource select line SSL, and the second select line may be a drain selectline DSL.

In detail, the memory block BLKa may include a plurality of stringscoupled between bit lines BL1 to BLn and a source line SL. The bit linesBL1 to BLn may be coupled to the strings, respectively, and the sourceline SL may be coupled in common to the strings. Because the strings maybe equally configured, a string ST coupled to the first bit line BL1will be described in detail by way of example.

The string ST may include a source select transistor SST, a plurality ofmemory cells F1 to F16, and a drain select transistor DST which arecoupled in series to each other between the source line SL and the firstbit line BL1. A single string ST may include at least one source selecttransistor SST and at least one drain select transistor DST, and morememory cells than the memory cells F1 to F16 illustrated in the drawingmay be included in the string ST.

A source of the source select transistor SST may be coupled to thesource line SL, and a drain of the drain select transistor DST may becoupled to the first bit line BL1. The memory cells F1 to F16 may becoupled in series between the source select transistor SST and the drainselect transistor DST. Gates of the source select transistors includedin different strings ST may be coupled to the source select line SSL,gates of the drain select transistors included in different strings STmay be coupled to the drain select line DSL, and gates of the memorycells F1 to F16 may be coupled to a plurality of word lines WL1 to WL16,respectively. A group of memory cells coupled to the same word line,among the memory cells included in different strings ST, may be referredto as a “physical page: PPG”. Therefore, the memory block BLKa mayinclude a number of physical pages PPG identical to the number of wordlines WL1 to WL16.

One memory cell may store one bit of data. This cell is typicallydesignated as a “single-level cell: SLC”. Here, one physical page PPGmay store data corresponding to one logical page LPG. The datacorresponding to one logical page LPG may include a number of data bitsidentical to the number of memory cells included in one physical pagePPG. Alternatively, one memory cell may store two or more bits of data.This cell is typically designated as a “multi-level cell: MLC”. Here,one physical page PPG may store data corresponding to two or morelogical pages LPG.

A memory cell in which two or more bits of data are stored is called amulti-level cell (MLC). However, recently, as the number of data bitsstored in one memory cell increases, the multi-level cell (MLC) refersto a memory cell in which two bits of data are stored, and thus a memorycell in which three bits of data are stored is called a triple-levelcell (TLC) and a memory cell in which four bits of data are stored iscalled a quadruple-level cell (QLC). In addition, a memory cell schemein which multiple bits of data are stored has been developed, and thepresent embodiment may be applied to the memory device 100 in which twoor more bits of data are stored.

In an embodiment, each of the memory blocks may have a three-dimensional(3D) structure. Each of the memory blocks may include a plurality ofmemory cells stacked on a substrate. The plurality of memory cells arearranged in +X, +Y, and +Z directions.

FIG. 4 is a diagram for describing the pin configuration of a memorydevice, for example, the memory device 100 of FIG. 1.

Referring to FIG. 4, the memory device 100 may communicate with anexternal controller through a plurality of data input/output lines. Forexample, the memory device 100 may communicate with the externalcontroller through control signal lines which include a chip enable lineCE #, a write enable line WE #, a read enable line RE #, an addresslatch enable line ALE, a command latch enable line CLE, a write protectline WP #, a ready/busy line RB, and data input/output lines DQ.

The memory device 100 may receive a chip enable signal from the externalcontroller through the chip enable line CE #. The memory device 100 mayreceive a write enable signal from the external controller through thewrite enable line WE #. The memory device 100 may receive a read enablesignal from the external controller through the read enable line RE #.The memory device 100 may receive an address latch enable signal fromthe external controller through the address latch enable line ALE. Thememory device 100 may receive a command latch enable signal from theexternal controller through the command latch enable line CLE. Thememory device 100 may receive a write protect signal from the externalcontroller through the write protect line WP #.

In an embodiment, the memory device 100 may provide the memorycontroller (e.g., 200 of FIG. 1) with a ready/busy signal, indicatingwhether the memory device 100 is in a ready state or in a busy state,through the ready/busy line RB.

The chip enable signal may be a control signal for selecting the memorydevice 100. When the chip enable signal is in a ‘high’ state and thememory device 100 is in a ‘ready’ state, the memory device 100 may entera low-power standby state.

The write enable signal may be a control signal for performing controlsuch that commands, addresses, and input data which are applied to thememory device 100 are stored in a latch.

The read enable signal may be a control signal for enabling the outputof serial data.

The address latch enable signal may be one of the control signals usedby the host to indicate which one of a command, an address, and datacorresponds to the type of signal input to the data input/output linesDQ.

The command latch enable signal may be one of the control signals usedby the host to indicate which one of a command, an address, and datacorresponds to the type of signal input to the data input/output linesDQ.

For example, when the command latch enable signal is activated (e.g., toa logic high state), the address latch enable signal is deactivated(e.g., to a logic low state), and the write enable signal is activated(e.g., to a logic low state) and then deactivated (e.g., to a logic highstate), the memory device 100 may identify that the signal input throughthe data input/output lines DQ is a command.

For example, when the command latch enable signal is deactivated (e.g.,to a logic low state), the address latch enable signal is activated(e.g., to a logic high state), and the write enable signal is activated(e.g., to a logic low state) and then deactivated (e.g., to a logic highstate), the memory device 100 may identify that the signal input throughthe data input/output lines DQ is an address.

The write protect signal may be a control signal for deactivating theprogram operation and the erase operation that are performed by thememory device 100.

The ready/busy signal may be a signal for identifying the status of thememory device 100. The ready/busy signal in a low state indicates thatthe memory device 100 is currently performing at least one operation.The ready/busy signal in a high state indicates that the memory device100 is currently performing no operation.

The ready/busy signal may be in a low state while the memory device 100is performing any one of a program operation, a read operation, and anerase operation. In an embodiment of the present disclosure, the memorycontroller 200, described with reference to FIG. 1, may determine atermination time point which is the time point at which the programoperation or the erase operation is terminated based on the ready/busysignal.

FIG. 5 is a diagram illustrating an embodiment in which a memory deviceand a test device are coupled to each other during a test operation.

Referring to FIG. 5, a configuration in which a memory device 100 and atest device TEST_DEVICE are coupled to each other through a plurality oflines during a test operation is illustrated in FIG. 5.

In an embodiment, in order to test the memory device 100, the memorydevice 100 and the test device TEST_DEVICE may be coupled to each otherthrough a probe card PROBE_CARD. For example, the probe card PROBE_CARDtransmits electricity while a probe needle mounted on the probe cardPROBE_CARD comes into contact with a wafer of the memory device 100, anddetermines whether the memory device 100 is defective depending on asignal returning from the memory device 100.

Here, the probe card PROBE_CARD and the memory device 100 may be coupledto each other through a plurality of lines.

Referring to FIG. 5, the probe card PROBE_CARD and the memory device 100may be coupled to each other through a command latch enable line CLE, anaddress latch enable line ALE, a write enable line WE #, a read enableline RE #, and input/output lines DQ<7:4> and DQ<3:0>.

In FIG. 5, the probe card PROBE_CARD and the memory device 100 may becoupled to each other through all of the input/output lines DQ<7:4> andDQ<3:0>. That is, in the present drawing, the input/output mode of thememory device 100 may be an X8 mode.

However, as the number of dies included in the memory device 100increases, the number of lines required in order to couple pins ofrespective dies to the probe card PROBE_CARD may increase. Also, as thenumber of required lines increases, related costs may also increase.

Therefore, in order to increase test efficiency, there is a need toreduce the number of lines for coupling the pins of respective dies tothe probe card PROBE_CARD while setting the input/output mode of thememory device 100 to the X4 mode.

The method of reducing the number of lines for coupling the pins ofrespective dies to the probe card PROBE_CARD will be described in detailbelow with reference to FIG. 6.

FIG. 6 is a diagram illustrating an embodiment in which a memory deviceand a test device are coupled to each other during a test operation.

Referring to FIG. 6, a configuration in which a memory device 100 and atest device TEST_DEVICE are coupled to each other through a plurality oflines during a test operation is illustrated in FIG. 6.

In FIG. 6, it is assumed that the memory device 100 is composed of twodies, each of the dies includes a plurality of planes, and each of theplanes includes a plurality of memory blocks. That is, the memory device100 of FIG. 6 may include a first die and a second die, and each of thefirst and second dies may include a plurality of planes, each includinga plurality of memory blocks.

In an embodiment, in order to test the memory device 100, the memorydevice 100 and the test device TEST_DEVICE may be coupled to each otherthrough a probe card PROBE_CARD. The probe card PROBE_CARD and thememory device 100 may be coupled to each other through a plurality oflines. The plurality of lines may include a command latch enable lineCLE, an address latch enable line ALE, a write enable line WE #, a readenable line RE #, and input/output lines DQ<7:4> and DQ<3:0> between theprobe card PROBE_CARD and the memory device 100.

However, unlike in FIG. 5, in FIG. 6, the probe card PROBE_CARD and thememory device 100 may be coupled to each other through some linesDQ<7:4> among the input/output lines DQ<7:4> and DQ<3:0>, and theinput/output mode of the memory device 100 may be the X4 mode.

In detail, through some lines DQ<7:4> through which upper bits of thedata input through the input/output lines are applied, the probe cardPROBE_CARD and the memory device 100 may be coupled to each other. Inthis case, among the dies included in the memory device 100, the firstdie may be coupled to the probe card PROBE_CARD through some linesDQ<7:4>.

That is, the lines DQ<3:0> through which lower bits of the data areapplied might not be coupled to the probe card PROBE_CARD, and the probecard PROBE_CARD and the first die may be coupled to each other throughthe lines DQ<7:4> through which the upper bits of the data are applied.In this case, the lines DQ<3:0>, which are other lines provided betweenthe probe card PROBE_CARD and the first die and through which lower bitsare applied, may be coupled to lines of the second die through whichupper bits are applied.

Therefore, because the lines related to the input of a command and anaddress may be shared between the first and second dies, and the probecard PROBE_CARD, which was coupled only to the first die, issimultaneously coupled both to the first and second dies, the number oflines for coupling the memory device 100 to the probe card PROBE_CARDmay be reduced. When the number of lines for coupling the memory device100 to the probe card PROBE_CARD is reduced, test performance may beimproved.

FIG. 7 illustrates a method in which data is input to a plurality ofdies during the test operation of FIG. 6.

Referring to FIGS. 6 and 7, FIG. 7 illustrates lines for coupling aprobe card PROBE_CARD and the memory device 100 to each other when thememory device 100 is in an X4 mode. The memory device 100 of FIG. 7 mayinclude a first die 101 and a second die 103, and each of the first andsecond dies 101 and 103 may include a plurality of planes, eachincluding a plurality of memory blocks.

In an embodiment, when the memory device is in the X4 mode, the firstand second dies 101 and 103 may share a command latch enable line CLE,an address latch enable line ALE, a write enable line WE #, and a readenable line RE # which are lines related to the input of a command andan address, with each other. Therefore, the memory device 100 mayperform a test operation on the first and second dies 101 and 103 duringthe test operation.

However, the first die 101 and the probe card PROBE_CARD may be coupledto each other through some lines DQ<7:4> through which upper bits areapplied, among the lines through which data is input to the first die101, and the second die 103 and the probe card PROBE_CARD may be coupledto each other through some lines DQ<7:4> through which upper bits areapplied, among the lines through which data is input to the second die103. Therefore, among the lines through which data is input to the firstand second dies 101 and 103, some lines DQ<3:0> through which lower bitsare applied might not be used.

In an embodiment, when the memory device 100 is in the X4 mode, the datamay be input through some lines DQ<7:4>, and thus the time required fordata input may be twice as long as the time required in the case wherethe memory device 100 is in the X8 mode. For example, a cycle duringwhich one piece of data is input in the X4 mode may be twice a cycleduring which one piece of data is input in the X8 mode.

As a result, as the cycle during which data is input increases, the timerequired for the test operation (test time) may also increase.

Therefore, in the present disclosure, there is presented a method ofreducing the test time in the X4 mode by controlling data so that thesame test as that performed in the X8 mode is enabled even in the X4mode.

FIG. 8 is a timing diagram illustrating a process in which a command, anaddress, and data are input in an X8 mode.

Referring to FIGS. 5 and 8, signals that are input through a pluralityof lines in the input/output mode of FIG. 5 are illustrated in FIG. 8.That is, FIG. 8 illustrates the input of data and internal input datainternally generated in a memory device, for example, the memory device100 of FIG. 5, when the memory device 100 uses all of input/output linesDQ<7:0> at the time of inputting/outputting data in an X8 mode.

In an embodiment, when a program operation is tested during a testoperation, the memory device 100 may receive a command latch enablesignal from an external controller through the command latch enable lineCLE. The command latch enable signal may be a signal indicating thatinput received through the input/output lines DQ<7:0> is a command.Therefore, when the command latch enable signal received through thecommand latch enable line CLE is in a high state, the input receivedthrough the input/output lines DQ<7:0> may be a command.

As a result, when the command latch enable signal is in a high state,command ‘80h’ may be received from the external controller.

Thereafter, when the reception of the command ‘80h’ is completed, thecommand latch enable signal may make a transition from a high state to alow state, and an address latch enable signal received through theaddress latch enable line ALE may make a transition to a high state.Here, the address latch enable signal may be a signal indicating thatinput received through the input/output lines DQ<7:0> is an address.Therefore, when the address latch enable signal received through theaddress latch enable line ALE is in a high state, the input receivedthrough the input/output lines DQ<7:0> may be an address.

As a result, when the address latch enable signal is in a high state,addresses ‘A1’, ‘A2’, ‘A3’, ‘A4’, and ‘A5’ may be received from theexternal controller.

Thereafter, when the reception of the addresses ‘A1’, ‘A2’, ‘A3’, ‘A4’,and ‘A5’ is completed, the address latch enable signal makes atransition from a high state to a low state, and a write enable signalreceived from the external controller through the write enable line WE #may make a transition from a high state to a low state. When the writeenable signal makes a transition to a low state, the memory device 100may receive data through the input/output lines DQ<7:0>. For example,when the write enable signal is in a low state, pieces of data ‘AA’,‘55’, ‘AA’, and ‘55’ may be received through the input/output linesDQ<7:0>.

Here, because the pieces of data are received using all of theinput/output lines DQ<7:0> coupled to the memory device 100, theexternally received data may be equally output as Internal input dataDQ_INT<7:0>, without being subjected to separate data control in thememory device 100. That is, the pieces of data received through theinput/output lines DQ<7:0> may be programmed, as the internal input dataDQ_INT<7:0>, to memory cells.

FIG. 9 is a timing diagram illustrating a process in which data is inputin an X4 mode.

Referring to FIGS. 6 and 9, FIG. 9 illustrates signals that are inputthrough a plurality of lines when a memory device, for example, thememory device 100 of FIG. 6, receives data from an external controllerin the input/output mode of FIG. 6. That is, FIG. 9 illustrates theinput of data and internal input data DQ_INT<7:0> internally generatedin the memory device 100 when the memory device 100 uses some of theinput/output lines DQ<7:0> in an X4 mode.

Referring to FIGS. 8 and 9, in FIG. 9, when the memory device 100receives a command and an address, it is operated in an X8 mode in whichall input/output lines DQ<7:0> are used in the same way as that of FIG.8, and thus a detailed description thereof will be omitted.

In an embodiment, the memory device 100 may receive data from anexternal controller when a write enable signal received through a writeenable line WE # is in a low state. Here, the memory device 100 mayreceive data through some input/output lines DQ<7:4> through which upperbits are applied, among the input/output lines DQ<7:0>. Therefore, amongthe input/output lines DQ<7:0>, some input/output lines DQ<3:0> throughwhich lower bits are applied might not be used.

Further, when a write protect signal received through a write protectline WP # is in a low state, the memory device 100 may receive datathrough some input/output lines DQ<7:4> through which upper bits areapplied, among the input/output lines DQ<7:0>.

Because the data is received through some input/output lines DQ<7:4>,among the input/output lines DQ<7:0>, pieces of data ‘A’, ‘A’, ‘5’, ‘5’,‘A’, ‘A’, ‘5’, and ‘5’ may be received through the input/output linesDQ<7:4> in the case where the write enable signal is in a low state whenthe memory device 100 is operated in the X4 mode. That is, because someinput/output lines DQ<3:0> through which lower bits are applied are notused, pieces of data ‘A’, ‘A’, ‘5’, ‘5’, ‘A’, ‘A’, ‘5’, and ‘5’ orpieces of data ‘A0’, ‘A0’, ‘50’, ‘50’, ‘A0’, ‘A0’, ‘50’, and ‘50’ may bereceived.

In this case, because the data is received through some input/outputlines DQ<7:4>, among all of the input/output lines DQ<7:0>, the timerequired to receive the data may be twice as long as the time requiredin FIG. 8. For example, when data is received through some input/outputlines DQ<7:4>, pieces of data ‘A0’, ‘A0’, ‘50’, and ‘50’ may be receivedduring a first cycle and data ‘A0’, ‘A0’, ‘50’, and ‘50’ may be receivedduring a second cycle. That is, data that can be received through all ofthe input/output lines DQ<7:0> during one cycle may be received throughsome input/output lines DQ<7:4> during two cycles.

In an embodiment, the memory device 100 may generate internal input dataDQ_INT<7:0> by internally combining the pieces of data ‘A0’, ‘A0’, ‘50’,‘50’, ‘A0’, ‘A0’, ‘50’, and ‘50’ received through some input/outputlines DQ<7:4>. For example, the memory device 100 may generate data ‘AA’by combining ‘A0’ with ‘A0’, and may generate data ‘55’ by combining‘50’ with ‘50’. The generated data may be programmed to the memory cellsof the memory device 100.

FIG. 10 illustrates a method of reducing a data input time in an X4mode.

Referring to FIGS. 6 and 10, FIG. 10 illustrates signals that are inputthrough a plurality of lines when a memory device, for example, thememory device 100 of FIG. 6, receives data from an external controllerin the input/output mode of FIG. 6. That is, FIG. 10 illustrates theinput of data and internal input data DQ_INT<7:0> internally generatedin the memory device 100 when the memory device 100 uses some of theinput/output lines DQ<7:0> in the X4 mode.

However, unlike in FIG. 9, in the present drawing, the memory device 100may receive all data during one cycle in the X4 mode.

In FIG. 9, because data is received through some input/output linesDQ<7:4>, among the input/output lines DQ<7:0>, a data input cycle may belengthened when the memory device 100 is operated in the X4 mode. Thatis, data that can be received during one cycle through all of theinput/output lines DQ<7:0> may be received during two cycles throughsome input/output lines DQ<7:4>. In detail, while a write enable signalreceived from the external controller through a write enable line WE #is in a low state, pieces of data ‘A0’, ‘A0’, ‘50’, and ‘50’ may bereceived through some input/output lines DQ<7:4> during one cycle. Here,‘0’ may mean that no data is input.

However, in the present drawing, even if data has been received throughsome input/output lines DQ<7:4>, the memory device 100 may internallygenerate input data based on the received data. For example, the memorydevice 100 may generate internal input data DQ_INT<7:0>, such as ‘AA’,‘AA’, ‘55’, and ‘55’, based on the pieces of data ‘A0’, ‘A0’, ‘50’, and‘50’ received through some input/output lines DQ<7:4>.

In an embodiment, when the memory device 100 internally generates inputdata, the same effect as when data is received through all input/outputlines DQ<7:0> may be obtained even if data is received through only someinput/output lines DQ<7:4> during one cycle.

The method of generating the internal input data DQ_INT<7:0> based onthe data received through some input/output lines DQ<7:4> will bedescribed below with reference to the following drawings.

FIGS. 11A to 11C illustrate methods in which data is input in an X4 modeand an X8 mode.

Referring to FIGS. 11A to 11C, FIG. 11A illustrates the configuration ofthe input controller of FIG. 1 (e.g., 170 of FIG. 1), FIG. 11Billustrates internal input data DQ_INT<7:0> generated by the inputcontroller 170 when a command or an address is input in the X4 mode, andFIG. 11C illustrates internal input data DQ_INT<7:0> generated by theinput controller 170 when data is input in the X4 mode.

In an embodiment, the input controller 170 may include a first gate 171,a second gate 173, and a multiplexer component 175. The multiplexercomponent 175 may include first to fourth multiplexers 175_1 to 175_4.The first gate 171 may be an OR gate (i.e., a logical OR gate), and thesecond gate 173 may be an AND gate (i.e., a logical AND gate).

In an embodiment, a normal mode signal X4_CURRENT and a fast mode signalX4_FASTLOAD may be input to the first gate 171. The normal mode signalX4_CURRENT may make a transition from a high state to a low state when amemory device, for example, the memory device 100, receives a command oran address from an external controller in the X4 mode. Also, the fastmode signal X4_FASTLOAD may make a transition from a low state to a highstate when the memory device 100 receives data from the externalcontroller in the X4 mode.

In an embodiment, when the normal mode signal X4_CURRENT in a high stateand/or the fast mode signal X4_FASTLOAD in a high state are input, thefirst gate 171 may output a high-state signal, whereas when the normalmode signal X4_CURRENT in a low state and the fast mode signalX4_FASTLOAD in a low state are input, the first gate 171 may output alow-state signal.

The high-state signal or the low-state signal output from the first gate171 may be input to the second gate 173. The signal output from thefirst gate 171 and a line enable signal TM_X4_MODE may be input to thesecond gate 173. The line enable signal TM_X4_MODE may be output fromthe mode setter 150 of FIG. 1.

For example, when the memory device 100 is operated in the X8 mode, theline enable signal TM_X4_MODE may be input as a low-state signal,whereas when the memory device 100 is operated in the X4 mode, the lineenable signal TM_X4_MODE may be input as a high-state signal. Therefore,when the memory device 100 is operated in the X4 mode, the line enablesignal TM_X4_MODE may be in a high state.

In an embodiment, when the normal mode signal X4_CURRENT in a low stateis input to the first gate 171, the externally received command oraddress may be output without change in the X4 mode. Further, when thefast mode signal X4_FASTLOAD in a high state is input to the first gate171, new internal input may be output based on externally received data.

In detail, when a command or an address is received in the X4 mode, theline enable signal TM_X4_MODE is in a high state, the normal mode signalX4_CURRENT is in a low state, and the fast mode signal X4_FASTLOAD is ina low state, and thus a low-state signal may be output from the firstgate 171. Because the signal output from the first gate 171 is alow-state signal, a low-state signal may be output from the second gate173 even if the line enable signal TM_X4_MODE is in a high state. Thelow-state signal output from the second gate 173 may be input to thefirst to fourth multiplexers 175_1 to 175_4.

When the low-state signal output from the second gate 173 is input tothe first to fourth multiplexers 175_1 to 1754, the multiplexercomponent 175 might not output the internal input data DQ_INT<3:0>. Thatis, when the memory device 100 receives a command or an address throughsome input/output lines DQ<7:4> in the X4 mode, the remaining linesDQ<3:0> other than some input/output lines DQ<7:4> might not be used,and the command or the address received through some input/output linesDQ<7:4> may be equally output as the internal input data DQ_INT<7:4>without being subjected to separate control.

Referring to FIG. 11B, the internal input data DQ_INT<7:0>, output fromthe first to fourth multiplexers 175_1 to 175_4 when the line enablesignal TM_X4_MODE is in a low state and the normal mode signalX4_CURRENT and the fast mode signal X4_FASTLOAD are in a low state, isillustrated. That is, the internal input data DQ_INT<3:0> might not begenerated, and the data received through some input/output lines DQ<7:4>may be output as the internal input data DQ_INT<7:4> without change.

Also, when data is received in the X4 mode, the line enable signalTM_X4_MODE is in a high state, the normal mode signal X4_CURRENT is in ahigh state, and the fast mode signal X4_FASTLOAD is in a high state, andthus a high-state signal may be output from the first gate 171. Becausethe signal output from the first gate 171 is in a high state and theline enable signal TM_X4_MODE is in a high state, a high-state signalmay be output from the second gate 173. The high-state signal outputfrom the second gate 173 may be input to the first to fourthmultiplexers 175_1 to 175_4.

When the high-state signal output from the second gate 173 is input tothe first to fourth multiplexers 175_1 to 175_4, the memory device 100may generate internal input data DQ_INT<3:0> based on the data receivedthrough some input/output lines DQ<7:4>. Here, the remaining linesDQ<3:0> other than the some input/output lines DQ<7:4> might not beused.

For example, internal input data DQ_INT<0> may be generated based onDQ<0> and DQ<4> that are input to the first multiplexer 175_1(MUX(DQ<0>, DQ<4>). Here, the first multiplexer 1751 may select DQ<4>between DQ<0> and DQ<4>, and may then output DQ<4> as the internal inputdata DQ_INT<0>.

Similarly, the second multiplexer 175_2 may select DQ<5> between inputDQ<1> and input DQ<5> and output DQ<5> as internal input data DQ_INT<1>(MUX(DQ<1>, DQ<5>), the third multiplexer 175_3 may select DQ<6> betweeninput DQ<2> and input DQ<6> and output DQ<6> as internal input dataDQ_INT<2> (MUX(DQ<2>, DQ<6>), and the fourth multiplexer 1754 may selectDQ<7> between input DQ<3> and input DQ<7> and may output DQ<7> asinternal input data DQ_INT<3> (MUX(DQ<3>, DQ<7>).

Referring to FIG. 11C, the internal input data, output from the first tofourth multiplexers 175_1 to 175_4 when the line enable signalTM_X4_MODE is in a high state and the normal mode signal X4_CURRENT andthe fast mode signal X4_FASTLOAD are in a high state, is illustrated.That is, although the remaining lines DQ<3:0> other than someinput/output lines DQ<7:4> are not used, the internal input dataDQ_INT<3:0> may be output from the first to fourth multiplexers 175_1 to175_4, and the data received through some input/output lines DQ<7:4> maybe output as the internal input data DQ_INT<7:4>.

Therefore, although the memory device 100 receives data through someinput/output lines DQ<7:4> in the X4 mode, data having the same size asthat when being operated in the X8 mode may be input in the same cycleas that in the X8 mode.

In other embodiments, when a memory device, for example, the memorydevice 100 of FIG. 6, is operated in the X8 mode, the line enable signalTM_X4_MODE may be in a low state. Therefore, regardless of the states ofthe normal mode signal X4_CURRENT and the fast mode signal X4_FASTLOAD,a low-state signal may be output from the second gate 173. Further, whenthe low-state signal output from the second gate 173 is input to thefirst to fourth multiplexers 175_1 to 175_4, the multiplexer component175 might not output the internal input data DQ_INT<3:0>. Furthermore,in the X8 mode, the internal input data DQ_INT<7:0> might not begenerated, and the memory device 100 may output data received throughthe input/output lines DQ<7:0> without change.

FIG. 12 illustrates control signals used for data input and generatedinternal input data in an X4 mode.

Referring to FIG. 12, a line enable signal TM_X4_MODE that is used toset the input mode of a memory device, for example, the memory device100, to an X4 mode or an X8 mode, a write enable signal that is inputthrough a write enable line WE #, data input DQ<7:0> that is inputthrough data input/output lines DQ, a write protect signal that is inputthrough a write protect line WP #, a fast mode signal X4_FASTLOAD thatindicates the input start and input end of data in the X4 mode, a firstcontrol signal TM_BIT_X4_FASTLOAD that is used to generate the fast modesignal X4_FASTLOAD, a second control signal DATA_IN_START, a thirdcontrol signal COLUMN_COUNTER_END, and internal input data DQ_INT<7:4>that is output from an input controller (e.g., 170 of FIG. 11) areillustrated in FIG. 12.

In FIG. 12, it is assumed that the memory device 100 receives data froman external controller in the X4 mode. Here, the X4 mode may be a modein which input is received from the external controller using only someof a greater number of input/output lines coupled to the memory device100, and the X8 mode may be a mode in which input is received from theexternal controller using all of the input/output lines coupled to thememory device 100.

In an embodiment, when the memory device 100 initiates operation in theX4 mode, the line enable signal TM_X4_MODE may make a transition from alow state to a high state. The line enable signal TM_X4_MODE may beoutput from the mode setter 150 of FIG. 1.

When the memory device 100 initiates operation in the X4 mode, data maybe received through some input/output lines DQ<7:4> when the writeprotect signal that is input through the write protect line WP # is in alow state. In the present drawing, because the memory device 100receives data from the external controller in the X4 mode, pieces ofdata ‘A0’, ‘50’, ‘A0’, and ‘50’ may be received through some input linesDQ<7:4>. The write protect signal that is input through the writeprotect line WP # while the data is input through some input/outputlines DQ<7:4> may be in a high state.

In an embodiment, the fast mode signal X4_FASTLOAD may indicate theinput start of data X4_MODE_START and the input end of data X4_MODE_ENDin the X4 mode. In an embodiment, the fast mode signal X4_FASTLOAD maybe generated based on the first control signal TM_BIT_X4_FASTLOAD, thesecond control signal DATA_IN_START, and the third control signalCOLUMN_COUNTER_END.

In detail, the first control signal TM_BIT_X4_FASTLOAD may make atransition from a low state to a high state when the input of data isstarted in the X4 mode. For example, in the present disclosure, when thememory device 100 internally generates input data in the X4 mode, thatis, when the input of data for allowing the input controller 170 tooutput the internal input data DQ_INT<7:0> is started, the first controlsignal TM_BIT_X4_FASTLOAD may make a transition from a low state to ahigh state.

The second control signal DATA_IN_START may make a transition from a lowstate to a high state when a data input command for instructing theinput of data is received from the external controller.

The third control signal COLUMN_COUNTER_END may make a transition from alow state to a high state when the input of data is terminated in the X4mode. For example, the third control signal COLUMN_COUNTER_END may makea transition to a high state when the last column of page data has beenreached at the time of inputting or outputting data.

In an embodiment, the fast mode signal X4_FASTLOAD may be generatedbased on the above-described first control signal TM_BIT_X4_FASTLOAD,second control signal DATA_IN_START, and third control signalCOLUMN_COUNTER_END. In detail, when the first control signalTM_BIT_X4_FASTLOAD is in a high state, the fast mode signal X4_FASTLOADmay be enabled by making a transition to a high state on the rising edgeof the second control signal DATA_IN_START, and may be disabled bymaking a transition to a low state on the rising edge of the thirdcontrol signal COLUMN_COUNTER_END. Therefore, the fast mode signalX4_FASTLOAD may indicate the input start of data X4_MODE_START and theinput end of data X4_MODE_END in the X4 mode.

In an embodiment, when the fast mode signal X4_FASTLOAD makes atransition from a low state to a high state, data may be receivedthrough some input/output lines DQ<7:4>. Here, the remaininginput/output lines DQ<3:0> other than some input/output lines DQ<7:4>might not be used. Alternatively, even if data has been input throughthe input/output lines DQ<3:0>, the corresponding data may be ignored.

Therefore, based on the data received through some input/output linesDQ<7:4>, the internal input data DQ_INT<7:0> may be output from theinput controller (e.g., 170 of FIG. 11). For example, although pieces ofdata ‘A0’, ‘50’, ‘A0’, and ‘50’ are actually received through someinput/output lines DQ<7:4>, the internal input data DQ_INT<7:0> may be‘AA’, ‘55’, ‘AA’, and ‘55’.

Consequently, although data is input through some input/output linesDQ<7:4> in the X4 mode, data having the same size as that when beingoperated in the X8 mode may be input in the same cycle as that in the X8mode. Therefore, in the X4 mode, a data input speed may be improved.

FIG. 13 illustrates the configuration of a control signal generator 190for generating the fast mode signal of FIG. 12.

Referring to FIG. 13, the control signal generator 190 of FIG. 13 mayinclude an input initiation signal generator 191, an input enable signalgenerator 193, an input disable signal generator 195, and a D flip-flop197. In FIG. 13, the control signal generator 190 may output the fastmode signal X4_FASTLOAD based on a line enable signal TM_X4_MODEreceived from the mode setter 150 of FIG. 1.

In an embodiment, the control signal generator 190 may receive the lineenable signal TM_X4_MODE from the mode setter 150 of FIG. 1. When thememory device (e.g., 100 of FIG. 6) initiates operation in the X4 mode,the line enable signal TM_X4_MODE may make a transition from a low stateto a high state. When the line enable signal TM_X4_MODE is received, theline enable signal TM_X4_MODE may be transferred to the input initiationsignal generator 191, the input enable signal generator 193, and theinput disable signal generator 195.

In an embodiment, the input initiation signal generator 191 may generatea first control signal TM_BIT_X4_FASTLOAD based on the line enablesignal TM_X4_MODE in a high state. The generated first control signalTM_BIT_X4_FASTLOAD may be input to an input pin D of the D flip-flop197.

The first control signal TM_BIT_X4_FASTLOAD output from the inputinitiation signal generator 191 may make a transition from a low stateto a high state when the input of data for allowing the input controller170 to output the internal input data DQ_INT<7:0> is started in the X4mode.

In an embodiment, the input enable signal generator 193 may generate asecond control signal DATA_IN_START based on the line enable signalTM_X4_MODE in a high state. The generated second control signalDATA_IN_START may be input to a clock pin CK of the D flip-flop 197.

The second control signal DATA_IN_START output from the input enablesignal generator 193 may make a transition from a low state to a highstate when a data input command for instructing the input of data isreceived from the external controller.

In an embodiment, the input disable signal generator 195 may generate athird control signal COLUMN_COUNTER_END based on the line enable signalTM_X4_MODE in a high state. The generated third control signalCOLUMN_COUNTER_END may be input to a reset pin R of the D flip-flop 197.

The third control signal COLUMN_COUNTER_END output from the inputdisable signal generator 195 may make a transition to a high state whenthe last column of page data has been reached at the time of inputtingor outputting data in the X4 mode.

In an embodiment, the D flip-flop 197 may output the fast mode signalX4_FASTLOAD through an output pin Q based on the first control signalTM_BIT_X4_FASTLOAD that is input through the input pin D.

In detail, when the first control signal TM_BIT_X4_FASTLOAD is inputthrough the input pin D of the D flip-flop 197, the fast mode signalX4_FASTLOAD may be enabled on the rising edge of the second controlsignal DATA_IN_START that is input through the clock pin CK. That is, onthe rising edge of the second control signal DATA_IN_START, the firstcontrol signal TM_BIT_X4_FASTLOAD may make a transition from a low stateto a high state.

Thereafter, when the third control signal COLUMN_COUNTER_END is inputthrough the reset pin R of the D flip-flop 197, the fast mode signalX4_FASTLOAD may be disabled on the rising edge of the third controlsignal COLUMN_COUNTER_END. That is, on the rising edge of the thirdcontrol signal COLUMN_COUNTER_END, the fast mode signal X4_FASTLOAD maymake a transition from a low state to a high state.

Consequently, because the fast mode signal X4_FASTLOAD is generatedbased on the first control signal TM_BIT_X4_FASTLOAD, the second controlsignal DATA_IN_START, and the third control signal COLUMN_COUNTER_END,the fast mode signal X4_FASTLOAD may indicate the input start of dataX4_MODE_START and the input end of data X4_MODE_END in the X4 mode.

FIG. 14 is a flowchart illustrating the operation of a memory deviceaccording to an embodiment of the present disclosure.

Referring to FIG. 14, at step S1401, the memory device may set a datainput mode to an X4 mode. Here, the X4 mode may be a mode in which inputis received from an external controller using only some of a greaternumber of input/output lines coupled to the memory device, and an X8mode may be a mode in which input is received from the externalcontroller using all of the input/output lines coupled to the memorydevice.

Therefore, when the mode of the memory device is set to the X4 mode,data may be received from the external controller through someinput/output lines at step S1403.

At step S1405, the memory device may generate internal input data basedon the data received through some input/output lines.

In an embodiment, when the memory device receives data in the X4 mode,an amount of time that is more than twice as long as the time used whendata is received in the X8 mode may be needed. Therefore, in the presentdisclosure, although the memory device receives data in the X4 mode, thememory device may internally generate internal input data based on thedata received through some input/output lines.

Through the above process, even if the memory device receives data inthe X4 mode, the memory device may receive data having the same amountas in the case of where data is received in the X8 mode in the samecycle as that in the X8 mode.

At step S1407, the memory device may perform a program operation basedon the internal input data. For example, the memory device may programthe internal input data to selected memory cells.

FIG. 15 is a diagram illustrating an embodiment of a memory controller,which for an embodiment, represents the memory controller 200 of FIG. 1.

A memory controller 1000 is coupled to a host and a memory device. Inresponse to a request received from the host, the memory controller 1000may access the memory device. For example, the memory controller 1000may be configured to control write, read, erase, and backgroundoperations of the memory device. The memory controller 1000 may providean interface between the memory device and the host. The memorycontroller 1000 may run firmware for controlling the memory device.

Referring to FIG. 15, the memory controller 1000 may include a processor1010, a memory buffer 1020, an error correction code (ECC) circuit 1030,a host interface 1040, a buffer control circuit 1050, a memory interface1060, and a bus 1070.

The bus 1070 may provide channels between components of the memorycontroller 1000.

The processor 1010 may control the overall operation of the memorycontroller 1000 and may perform logical operations. The processor 1010may communicate with an external host through the host interface 1040and also communicate with the memory device through the memory interface1060. Further, the processor 1010 may communicate with the memory buffer1020 through the buffer control circuit 1050. The processor 1010 maycontrol the operation of the storage device by using the memory buffer1020 as working memory, cache memory, or buffer memory.

The processor 1010 may perform the function of a flash translation layer(FTL). The processor 1010 may translate a logical block address (LBA),provided by the host, into a physical block address (PBA) through theFTL. The FTL may receive the LBA using a mapping table and translate theLBA into the PBA. Examples of an address mapping method performedthrough the FTL may include various methods according to a mapping unit.Representative address mapping methods include a page mapping method, ablock mapping method, and a hybrid mapping method.

The processor 1010 may randomize data received from the host. Forexample, the processor 1010 may use a randomizing seed to randomize datareceived from the host. The randomized data may be provided, as data tobe stored, to the memory device and may be programmed in the memory cellarray.

The processor 1010 may run software or firmware to perform therandomizing or derandomizing operation.

In an embodiment, the processor 1010 may run software or firmware toperform randomizing and derandomizing operations.

The memory buffer 1020 may be used as working memory, cache memory, orbuffer memory of the processor 1010. The memory buffer 1020 may storecodes and commands executed by the processor 1010. The memory buffer1020 may store data that is processed by the processor 1010. The memorybuffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

The ECC circuit 1030 may perform error correction. The ECC circuit 1030may perform error correction code (ECC) encoding based on data to bewritten to the memory device through the memory interface 1060. TheECC-encoded data may be transferred to the memory device through thememory interface 1060. The ECC circuit 1030 may perform ECC decodingbased on data received from the memory device through the memoryinterface 1060. In an example, the ECC circuit 1030 may be included as acomponent of the memory interface 1060 in the memory interface 1060.

The host interface 1040 may communicate with the external host under thecontrol of the processor 1010. The host interface 1040 may performcommunication using at least one of various communication methods suchas Universal Serial Bus (USB), Serial AT Attachment (SATA), SerialAttached SCSI (SAS), High Speed Interchip (HSIC), Small Computer SystemInterface (SCSI), Peripheral Component Interconnection (PCI), PCIexpress (PCIe), Nonvolatile Memory express (NVMe), Universal FlashStorage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC(eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), andLoad Reduced DIMM (LRDIMM) communication methods.

The buffer control circuit 1050 may control the memory buffer 1020 underthe control of the processor 1010.

The memory interface 1060 may communicate with the memory device underthe control of the processor 1010. The memory interface 1060 maytransmit/receive commands, addresses, and data to/from the memory devicethrough channels.

In an embodiment, the memory controller 1000 might not include thememory buffer 1020 and the buffer control circuit 1050.

In an embodiment, the processor 1010 may control the operation of thememory controller 1000 using codes. The processor 1010 may load codesfrom a nonvolatile memory device (e.g., ROM) provided in the memorycontroller 1000. In an embodiment, the processor 1010 may load codesfrom the memory device through the memory interface 1060.

In an embodiment, the bus 1070 of the memory controller 1000 may bedivided into a control bus and a data bus. The data bus may beconfigured to transmit data in the memory controller 1000, and thecontrol bus may be configured to transmit control information such ascommands or addresses in the memory controller 1000. The data bus andthe control bus may be isolated from each other, and may neitherinterfere with each other nor influence each other. The data bus may becoupled to the host interface 1040, the buffer control circuit 1050, theECC circuit 1030, and the memory interface 1060. The control bus may becoupled to the host interface 1040, the processor 1010, the buffercontrol circuit 1050, the memory buffer 1020, and the memory interface1060.

FIG. 16 is a block diagram illustrating a memory card system to whichthe storage device according to an embodiment of the present disclosureis applied.

Referring to FIG. 16, a memory card system 2000 may include a memorycontroller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is coupled to the memory device 2200. Thememory controller 2100 may access the memory device 2200. For example,the memory controller 2100 may control read, write, erase, andbackground operations of the memory device 2200. The memory controller2100 may provide an interface between the memory device 2200 and a host.The memory controller 2100 may run firmware for controlling the memorydevice 2200. The memory device 2200 may be implemented in the same wayas the memory device (e.g., 100 of FIG. 1) described above withreference to FIG. 1.

In an embodiment, the memory controller 2100 may include components,such as RAM, a processor, a host interface, a memory interface, and anECC circuit.

The memory controller 2100 may communicate with an external devicethrough the connector 2300. The memory controller 2100 may communicatewith an external device (e.g., a host) based on a specific communicationprotocol. In an embodiment, the memory controller 2100 may communicatewith the external device through at least one of various communicationprotocols such as universal serial bus (USB), multi-media card (MMC),embedded MMC (eMMC), peripheral component interconnection (PCI),PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA(SATA), parallel-ATA (PATA), small computer system interface (SCSI),enhanced small disk interface (ESDI), integrated drive electronics(IDE), Firewire, universal flash storage (UFS), Wi-Fi, Bluetooth, andnonvolatile memory express (NVMe) protocols. In an embodiment, theconnector 2300 may be defined by at least one of the above-describedvarious communication protocols.

In an embodiment, the memory device 2200 may be implemented as any ofvarious nonvolatile memory devices including, for example, ElectricallyErasable and Programmable ROM (EEPROM), NAND flash memory, NOR flashmemory, Phase-change RAM (PRAM), Resistive RAM (ReRAM), FerroelectricRAM (FRAM), or Spin Transfer Torque Magnetic RAM (STT-MRAM).

The memory controller 2100 and the memory device 2200 may be integratedinto a single semiconductor device to configure a memory card. Forexample, the memory controller 2100 and the memory device 2200 may beintegrated into a single semiconductor device to configure a memory cardsuch as a PC card (personal computer memory card internationalassociation: PCMCIA), a compact flash card (CF), a smart media card (SMor SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro oreMMC), an SD card (SD, miniSD, microSD, or SDHC), or universal flashstorage (UFS).

In an embodiment, the memory device 2200 may receive data from thememory controller 2100 using some of a plurality of input/output linescoupled to the memory device 2200. Here, assuming that the total numberof input/out lines is eight, a data input mode may be the X8 mode whendata is received through all eight of the input/output lines, and may bethe X4 mode when data is received through only four of the eightinput/output lines.

In an embodiment, when the memory device 2200 receives data in the X4mode, a longer time may be taken compared to the case where data isreceived in the X8 mode. Therefore, when data is received in the X4mode, the memory device 2200 may generate internal input data based onthe data received through some input/output lines.

In an embodiment, the memory device 2200 may receive input such that thecase where a command or an address is received from the memorycontroller 2100 in the X4 mode is distinguished from the case where datais received in the X4 mode.

For example, when a command or address is received from the memorycontroller 2100 in the X4 mode, the memory device 2200 may receive thecommand or the address through some input/output lines, and might notinternally generate an internal input command or an internal inputaddress. That is, when the command or the address is received in the X4mode, generation of internal input data by the memory device 2200 may beskipped.

However, when data is received from the memory controller 2100 in the X4mode, the memory device 2200 may receive data through some input/outputlines, and may generate internal input data based on the received data.The received data may be generated as internal input data through amultiplexer component (e.g., 175 of FIG. 11).

FIG. 17 is a block diagram illustrating an example of a solid statedrive (SSD) system to which a storage device according to an embodimentof the present disclosure is applied.

Referring to FIG. 17, an SSD system 3000 may include a host 3100 and anSSD 3200. The SSD 3200 may exchange signals SIG with the host 3100through a signal connector 3001 and may receive power PWR through apower connector 3002. The SSD 3200 may include an SSD controller 3210, aplurality of flash memories 3221 to 322 n, an auxiliary power supply3230, and a buffer memory 3240. Here, the flash memory representsnon-volatile memory NVM.

In an embodiment, the SSD controller 3210 may perform the function ofthe memory controller (e.g., 200 of FIG. 1) described above withreference to FIG. 1.

The SSD controller 3210 may control the plurality of flash memories 3221to 322 n in response to the signals SIG received from the host 3100. Inan embodiment, the signals SIG may be signals based on the interfaces ofthe host 3100 and the SSD 3200. For example, the signals SIG may besignals defined by at least one of various interfaces such as universalserial bus (USB), multi-media card (MMC), embedded MMC (eMMC),peripheral component interconnection (PCI), PCI-express (PCI-E),advanced technology attachment (ATA), serial-ATA (SATA), parallel-ATA(PATA), small computer system interface (SCSI), enhanced small diskinterface (ESDI), integrated drive electronics (IDE), Firewire,universal flash storage (UFS), Wi-Fi, Bluetooth, and nonvolatile memoryexpress (NVMe) interfaces.

The auxiliary power supply 3230 may be coupled to the host 3100 throughthe power connector 3002. The auxiliary power supply 3230 may besupplied with power PWR from the host 3100 and may be charged. Theauxiliary power supply 3230 may supply the power of the SSD 3200 whenthe supply of power from the host 3100 is not smoothly performed. In anembodiment, the auxiliary power supply 3230 may be positioned inside theSSD 3200 or positioned outside the SSD 3200. For example, the auxiliarypower supply 3230 may be disposed in a main board and may supplyauxiliary power to the SSD 3200.

The buffer memory 3240 functions as a buffer memory of the SSD 3200. Forexample, the buffer memory 3240 may temporarily store data received fromthe host 3100 or data received from the plurality of flash memories 3221to 322 n or may temporarily store metadata (e.g., mapping tables) of theflash memories 3221 to 322 n. The buffer memory 3240 may includevolatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAMor nonvolatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

In an embodiment, each of the plurality of flash memories 3221 to 322 nmay receive data from the SSD controller 3210 using some of a pluralityof input/output lines. Here, assuming that the total number of input/outlines is eight, a data input mode may be the X8 mode when data isreceived through all eight of the input/output lines, and may be the X4mode when data is received through only four of the eight input/outputlines.

In an embodiment, when the plurality of flash memories 3221 to 322 nreceive data in the X4 mode, a longer time may be taken compared to thecase where data is received in the X8 mode. Therefore, when theplurality of flash memories 3221 to 322 n receive data in the X4 mode,each of the flash memories 3221 to 322 n may generate internal inputdata based on the data received through some input/output lines.

In an embodiment, each of the flash memories 3221 to 322 n may receiveinput such that the case where the command or address is received fromthe SSD controller 3210 in the X4 mode is distinguished from the casewhere data is received in the X4 mode.

For example, when the command or address is received from the SSDcontroller 3210 in the X4 mode, each of the plurality of flash memories3221 to 322 n may receive the command or the address through someinput/output lines, and might not internally generate an internal inputcommand or an internal input address. That is, when the command or theaddress is received in the X4 mode, generation of internal input data byeach of the flash memories 3221 to 322 n may be skipped.

However, when data is received from the SSD controller 3210 in the X4mode, each of the flash memories 3221 to 322 n may receive data throughsome input/output lines, and may generate internal input data based onthe received data. The received data may be generated as internal inputdata through a multiplexer component (e.g., 175 of FIG. 11).

FIG. 18 is a block diagram illustrating a user system to which thestorage device according to an embodiment of the present disclosure isapplied.

Referring to FIG. 18, a user system 4000 may include an applicationprocessor 4100, a memory module 4200, a network module 4300, a storagemodule 4400, and a user interface 4500.

The application processor 4100 may run components included in the usersystem 4000, an Operating System (OS) or a user program. In anembodiment, the application processor 4100 may include controllers,interfaces, graphic engines, etc. for controlling the componentsincluded in the user system 4000. The application processor 4100 may beprovided as a system-on-chip (SoC).

The memory module 4200 may function as main memory, working memory,buffer memory, or cache memory of the user system 4000. The memorymodule 4200 may include volatile RAMs such as DRAM, SDRAM, DDR SDRAM,DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, ornonvolatile RAMs such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment,the application processor 4100 and the memory module 4200 may bepackaged based on package-on-package (POP) and may then be provided as asingle semiconductor package.

The network module 4300 may communicate with external devices. Forexample, the network module 4300 may support wireless communication,such as Code Division Multiple Access (CDMA), Global System for Mobilecommunication (GSM), wideband CDMA (WCDMA), CDMA-2000, Time DivisionMultiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB,Bluetooth, or Wi-Fi communication. In an embodiment, the network module4300 may be included in the application processor 4100.

The storage module 4400 may store data. For example, the storage module4400 may store data received from the application processor 4100.Alternatively, the storage module 4400 may transmit the data stored inthe storage module 4400 to the application processor 4100. In anembodiment, the storage module 4400 may be implemented as a nonvolatilesemiconductor memory device including Phase-change RAM (PRAM), MagneticRAM (MRAM), Resistive RAM (RRAM), NAND flash memory, NOR flash memory,or NAND flash memory having a three-dimensional (3D) structure. In anembodiment, the storage module 4400 may be provided as a removablestorage medium (i.e., removable drive), such as a memory card or anexternal drive of the user system 4000.

In an embodiment, the storage module 4400 may include a plurality ofnonvolatile memory devices, each of which may be operated in the sameway as the memory device described above with reference to FIGS. 2 and3. The storage module 4400 may be operated in the same way as thestorage device 50 described above with reference to FIG. 1.

The user interface 4500 may include interfaces which input data orinstructions to the application processor 4100 or output data to anexternal device. In an embodiment, the user interface 4500 may includeuser input interfaces such as a keyboard, a keypad, a button, a touchpanel, a touch screen, a touch pad, a touch ball, a camera, amicrophone, a gyroscope sensor, a vibration sensor, and a piezoelectricdevice. The user interface 4500 may further include user outputinterfaces such as a Liquid Crystal Display (LCD), an Organic LightEmitting Diode (OLED) display device, an Active Matrix OLED (AMOLED)display device, an LED, a speaker, and a monitor.

In an embodiment, the storage module 4400 may receive data from theapplication processor 4100 using some of a plurality of input/outputlines coupled to the storage module 4400. Here, assuming that the totalnumber of input/out lines is eight, a data input mode may be the X8 modewhen data is received through all of the input/output lines, and may bethe X4 mode when data is received through only four of the eightinput/output lines.

In an embodiment, when the storage module 4400 receives data in the X4mode, a longer time may be taken compared to the case where data isreceived in the X8 mode. Therefore, when data is received in the X4mode, the storage module 4400 may generate internal input data based onthe data received through some input/output lines.

In an embodiment, the storage module 4400 may receive input such thatthe case where a command or an address is received from the applicationprocessor 4100 in the X4 mode is distinguished from the case where datais received in the X4 mode.

For example, when the command or address is received from theapplication processor 4100 in the X4 mode, the storage module 4400 mayreceive the command or the address through some input/output lines, andmight not internally generate an internal input command or an internalinput address. That is, when the command or the address is received inthe X4 mode, generation of internal input data by the storage module4400 may be skipped.

However, when data is received from the application processor 4100 inthe X4 mode, the storage module 4400 may receive data through someinput/output lines, and may generate internal input data based on thereceived data. The received data may be generated as internal input datathrough a multiplexer component (e.g., 175 of FIG. 11).

In accordance with the present disclosure, data input is controlled suchthat data is input in one clock when data is input using only some of agreater number of input/output lines, and thus the time required fordata input may be reduced.

What is claimed is:
 1. A memory device, comprising: a plurality ofpages; a peripheral circuit configured to receive a command, an address,and data from an external controller to program a page selected fromamong the plurality of pages, and to generate internal input datadepending on an input mode for the command, the address, and the data;and control logic configured to determine whether internal input data isto be generated based on the data depending on the input mode and tocontrol the peripheral circuit so that a program operation ofprogramming the internal input data is performed.
 2. The memory deviceaccording to claim 1, wherein the input mode is one of: a first mode inwhich the command, the address, and the data are received through all ofthe plurality of input/output lines; and a second mode in which thecommand, the address, and the data are received through only some of theplurality of input/output lines.
 3. The memory device according to claim2, wherein the peripheral circuit is configured to perform, when thecommand or the address is received from the external controller in acase where the input mode is the first mode, the program operation basedon the received command or address.
 4. The memory device according toclaim 2, wherein the peripheral circuit is configured to generate, whenthe data is received from the external controller in a case where theinput mode is the second mode, the internal input data.
 5. The memorydevice according to claim 2, wherein the peripheral circuit isconfigured to generate, when the input mode is the second mode, theinternal input data by combining first input data indicating the datawith second input data, wherein the second input data is selected andoutput based on the data and input of remaining lines of the pluralityof input/output lines other than the some of the plurality ofinput/output lines.
 6. A memory device, comprising: a plurality ofpages; a mode setter configured to set a mode in which a command, anaddress, and data are received from an external controller to program apage selected from among the plurality of pages; an input controllerconfigured to generate internal input data based on the data dependingon the mode set by the mode setter; and a control signal generatorconfigured to generate a control signal for controlling the inputcontroller to generate the internal input data.
 7. The memory deviceaccording to claim 6, wherein the mode setter is configured to output aline enable signal for setting one of: a first mode in which thecommand, the address, and the data are received through all of theplurality of input/output lines; and a second mode in which the command,the address, and the data are received through only some of theplurality of input/output lines.
 8. The memory device according to claim7, wherein the mode setter is configured to output the line enablesignal in a high state to the control signal generator to set the secondmode.
 9. The memory device according to claim 8, wherein the controlsignal generator comprises: an input initiation signal generatorconfigured to generate a first control signal indicating that input ofthe data is initiated based on the line enable signal in a high state;an input enable signal generator configured to generate a second controlsignal indicating that a data input command for instructing input of thedata has been received from the external controller; an input disablesignal generator configured to generate, when the data is input, a thirdcontrol signal indicating that a last column of data in the selectedpage has been reached; and a D flip-flop configured to output a fastmode signal for instructing generation of the internal input data basedon the first, second, and third control signals.
 10. The memory deviceaccording to claim 9, wherein the fast mode signal indicates an inputstart and an input end of the data.
 11. The memory device according toclaim 9, wherein the input initiation signal generator is configured tooutput the first control signal to an input pin of the D flip-flop. 12.The memory device according to claim 9, wherein the input enable signalgenerator is configured to output the second control signal to a clockpin of the D flip-flop.
 13. The memory device according to claim 12,wherein the D flip-flop is configured to enable the fast mode signal ona rising edge of the second control signal.
 14. The memory deviceaccording to claim 9, wherein the input disable signal generator isconfigured to output the third control signal to a reset pin of the Dflip-flop.
 15. The memory device according to claim 14, wherein the Dflip-flop is configured to disable the fast mode signal on a rising edgeof the third control signal.
 16. The memory device according to claim 7,wherein the input controller is configured to generate, when the controlsignal in a high state is received from the control signal generator,the internal input data by combining first input data indicating thedata with second input data, wherein the second input data is selectedand output based on the data and input of remaining lines of theplurality of input/output lines other than the some of the plurality ofinput/output lines.
 17. A method of operating a memory device,comprising: setting a mode in which a command, an address, and data arereceived from an external controller to program a page selected fromamong a plurality of pages; receiving the data based on the set mode;generating a control signal for generating internal input data based onthe data depending on the set mode; and generating the internal inputdata based on the control signal.
 18. The method according to claim 17,wherein setting the mode comprises: setting the mode to a first mode inwhich the command, the address, and the data are received through all ofthe plurality of input/output lines; or setting the mode to a secondmode in which the command, the address, and the data are receivedthrough only some of the plurality of input/output lines.
 19. The methodaccording to claim 18, wherein generating the control signal comprisesgenerating, when the data is received in the second mode, a fast modesignal indicating an input start and an input end of the data.
 20. Themethod according to claim 18, wherein generating the internal input datacomprises generating, when the control signal in a high state isgenerated in the second mode, the internal input data by combining firstinput data indicating the data with second input data, wherein thesecond input data is selected and output based on the data and input ofremaining lines of the plurality of input/output lines other than thesome of the plurality of input/output lines.